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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>CTERMEQ, CTERMNE</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CTERMEQ, CTERMNE</h2><p>Compare and terminate loop</p>
      <p class="aml">Detect termination conditions in serialized vector loops. Tests whether the comparison between the scalar source operands holds true and if not tests the state of the <span class="arm-defined-word">!Last</span> condition flag (C) which indicates whether the previous flag-setting predicate instruction selected the last element of the vector partition.</p>
      <p class="aml">The Z and C condition flags are preserved by this instruction. The N and V condition flags are set as a pair to generate one of the following conditions for a subsequent conditional instruction:</p>
      <p class="aml"/>
      <table class="valuetable">
        
          <thead>
            <tr>
              <th class="">Condition</th>
              <th class="">N</th>
              <th class="">V</th>
              <th class="">Meaning</th>
            </tr>
          </thead>
          <tbody>
            <tr>
              <td class="">GE</td>
              <td class="">0</td>
              <td class="">0</td>
              <td class="">Continue loop (compare failed and last element not selected)</td>
            </tr>
            <tr>
              <td class="">LT</td>
              <td class="">0</td>
              <td class="">1</td>
              <td class="">Terminate loop (last element selected)</td>
            </tr>
            <tr>
              <td class="">LT</td>
              <td class="">1</td>
              <td class="">0</td>
              <td class="">Terminate loop (compare succeeded)</td>
            </tr>
            <tr>
              <td class="">GE</td>
              <td class="">1</td>
              <td class="">1</td>
              <td class="">Never generated</td>
            </tr>
          </tbody>
        
      </table>
      <p class="aml">The scalar source operands are 32-bit or 64-bit general-purpose registers of the same size.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_eq">Equal</a>
       and 
      <a href="#iclass_ne">Not equal</a>
    </p>
    <h3 class="classheading"><a id="iclass_eq"/>Equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">sz</td><td class="lr">1</td><td colspan="5" class="lr">Rm</td><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td colspan="5" class="lr">Rn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="6"/><td/><td/><td/><td colspan="5"/><td colspan="6"/><td colspan="5"/><td class="droppedname">ne</td><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="ctermeq_rr_"/><p class="asm-code">CTERMEQ <a href="#sa_r" title="Width specifier (field &quot;sz&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_n" title="Source general-purpose register number [0-30] or ZR (31) (field &quot;Rn&quot;)">&lt;n&gt;</a>, <a href="#sa_r" title="Width specifier (field &quot;sz&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_m" title="Source general-purpose register number [0-30] or ZR (31) (field &quot;Rm&quot;)">&lt;m&gt;</a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 32 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a>;</p>
    <h3 class="classheading"><a id="iclass_ne"/>Not equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">sz</td><td class="lr">1</td><td colspan="5" class="lr">Rm</td><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td colspan="5" class="lr">Rn</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="6"/><td/><td/><td/><td colspan="5"/><td colspan="6"/><td colspan="5"/><td class="droppedname">ne</td><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="ctermne_rr_"/><p class="asm-code">CTERMNE <a href="#sa_r" title="Width specifier (field &quot;sz&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_n" title="Source general-purpose register number [0-30] or ZR (31) (field &quot;Rn&quot;)">&lt;n&gt;</a>, <a href="#sa_r" title="Width specifier (field &quot;sz&quot;) [W,X]">&lt;R&gt;</a><a href="#sa_m" title="Source general-purpose register number [0-30] or ZR (31) (field &quot;Rm&quot;)">&lt;m&gt;</a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() &amp;&amp; !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 32 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a>;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;R&gt;</td><td><a id="sa_r"/>
        <p>Is a width specifier, 
      encoded in
      <q>sz</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">sz</th>
                <th class="symbol">&lt;R&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">W</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">X</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;n&gt;</td><td><a id="sa_n"/>
        
          <p class="aml">Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;m&gt;</td><td><a id="sa_m"/>
        
          <p class="aml">Is the number [0-30] of the source general-purpose register or the name ZR (31), encoded in the "Rm" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
bits(esize) operand1 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, esize];
bits(esize) operand2 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, esize];
integer element1 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(operand1);
integer element2 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(operand2);
boolean term;

case op of
    when <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a> term = element1 == element2;
    when <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a> term = element1 != element2;
if term then
    PSTATE.N = '1';
    PSTATE.V = '0';
else
    PSTATE.N = '0';
    PSTATE.V = (NOT PSTATE.C);</p>
    </div>
  <h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
              The values of the data supplied in any of its registers.
            </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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